【摘要】：隨著人們對海洋開發(fā)投入的增加,基于矢量水聽器陣列的目標(biāo)探測系統(tǒng)的研究受到了越來越多的重視。信號預(yù)處理分機作為目標(biāo)探測系統(tǒng)的重要組成部分,承擔(dān)著信號調(diào)理、采集、緩存以及數(shù)據(jù)傳輸?shù)戎匾ぷ�。隱身及減振降噪技術(shù)的發(fā)展,對目標(biāo)探測系統(tǒng)的預(yù)處理分機提出了更高的要求。本文設(shè)計并實現(xiàn)了矢量陣目標(biāo)探測系統(tǒng)信號預(yù)處理分機,主要采用FPGA及Nios Ⅱ處理器來完成全部工作。本論文完成了矢量陣目標(biāo)探測系統(tǒng)信號預(yù)處理分機硬件設(shè)計與軟件調(diào)試。首先,根據(jù)系統(tǒng)設(shè)計提出的需求,按照其功能與任務(wù)的差異,本文模塊化地對硬件進(jìn)行了設(shè)計,包括芯片選型、電路原理圖的設(shè)計,PCB的設(shè)計。硬件主要包括信號調(diào)理電路、網(wǎng)絡(luò)供電電路、數(shù)據(jù)采集電路和以太網(wǎng)接口電路。其次,在FPGA平臺上搭載了以Nios Ⅱ及外圍接口為核心的片上系統(tǒng),實現(xiàn)了TSE_MAC+PHY架構(gòu)的網(wǎng)絡(luò)數(shù)據(jù)傳輸模塊,基于Avalon總線規(guī)范添加了自定義FIFO與RAM,對電源電路、AD采集時序、數(shù)據(jù)緩存時序以及以太網(wǎng)接口模塊進(jìn)行了調(diào)試隨后,編寫了數(shù)據(jù)緩存的管理邏輯與以太網(wǎng)數(shù)據(jù)傳輸?shù)某绦颉１驹O(shè)計通過FPGA實現(xiàn)AD芯片的控制邏輯,對13路信號進(jìn)行實時采樣與緩存,利用Nios Ⅱ處理器對緩存的數(shù)據(jù)進(jìn)行傳輸,最終傳輸至上位機的硬盤,以文件的形式保存。最后,本文對預(yù)處理平臺進(jìn)行了測試與驗證,包括AD采樣的測試,數(shù)據(jù)接收存儲的測試、以太網(wǎng)的聯(lián)合測試、羅經(jīng)數(shù)據(jù)傳輸?shù)臏y試和湖上實驗。在文章的結(jié)尾,總結(jié)設(shè)計的經(jīng)驗與不足,明確了改進(jìn)的方向,為更好地發(fā)揮矢量陣目標(biāo)探測系統(tǒng)的效能做出準(zhǔn)備。
[Abstract]:With the increasing investment in ocean development, more and more attention has been paid to the research of target detection system based on vector hydrophone array. As an important part of the target detection system, the signal preprocessing extension is responsible for signal conditioning, acquisition, buffer and data transmission. With the development of stealth and vibration reduction and noise reduction technology, the preprocessing extension of target detection system is required higher. In this paper, the signal preprocessing extension of vector array target detection system is designed and implemented, which mainly uses FPGA and Nios 鈪，

本文編號：2348282