本文選題：數(shù)字雷達(dá)專用芯片　切入點(diǎn)：可編程門陣列　出處：《西安電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

【摘要】：數(shù)字雷達(dá)系統(tǒng)由于其高精度幅相正交特性、抗干擾性、穩(wěn)定性等優(yōu)勢(shì)已經(jīng)成為新一代雷達(dá)體系的主要發(fā)展方向，被更多的應(yīng)用到全天候遠(yuǎn)距離實(shí)現(xiàn)對(duì)目標(biāo)的探測(cè)和定位，在軍事民用領(lǐng)域如民航交通管制、陸�？毡O(jiān)視、精確制導(dǎo)、導(dǎo)航、汽車防撞與測(cè)距以及氣象預(yù)報(bào)等眾多國(guó)民經(jīng)濟(jì)重要部門。同時(shí)在微電子技術(shù)日新月異的發(fā)展中，F(xiàn)PGA和DSP在信號(hào)處理能力上不斷提升，ASIC即專用集成電路能夠?qū)崿F(xiàn)比DSP和FPGA處理速度更快，功耗更低及更高的可靠性，并擁有自主知識(shí)產(chǎn)權(quán)的芯片大規(guī)�；a(chǎn)后在價(jià)格上具有很大的優(yōu)勢(shì)。因此利用最新的片上芯片系統(tǒng)（System on Chip）技術(shù)來設(shè)計(jì)新一代體制的數(shù)字雷達(dá)系統(tǒng)成為目前研究的當(dāng)務(wù)之急。 本論文的工作來源于部委研究項(xiàng)目，重點(diǎn)研究數(shù)字雷達(dá)接收機(jī)信號(hào)處理的IP核設(shè)計(jì),并且就數(shù)據(jù)通路的性能優(yōu)化、面積優(yōu)化、驗(yàn)證平臺(tái)等方面展開了研究和設(shè)計(jì)實(shí)現(xiàn)工作。主要討論了流水式數(shù)字信號(hào)處理器和時(shí)分復(fù)用方式的電路實(shí)現(xiàn)架構(gòu)。并在時(shí)分復(fù)用方式下對(duì)性能優(yōu)化與電路優(yōu)化兩個(gè)方面進(jìn)行討論并設(shè)計(jì)了數(shù)據(jù)通路。并且最終實(shí)現(xiàn)了兩個(gè)優(yōu)化條件下的數(shù)據(jù)通路框架設(shè)計(jì)。 本論文工作在雷達(dá)接收通道SoC原型系統(tǒng)設(shè)計(jì)實(shí)驗(yàn)和板級(jí)驗(yàn)證平臺(tái)的實(shí)現(xiàn)基礎(chǔ)上，對(duì)主要雷達(dá)信號(hào)進(jìn)行了驗(yàn)證測(cè)試。測(cè)試數(shù)據(jù)結(jié)果表明功能滿足要求。在SMIC0.13um工藝下，性能優(yōu)化中最高中頻信號(hào)吞吐率為2GSPS，，面積優(yōu)化中數(shù)據(jù)通路面積約0.05mm2。實(shí)驗(yàn)結(jié)果說明本系統(tǒng)設(shè)計(jì)和驗(yàn)證平臺(tái)達(dá)到了項(xiàng)目設(shè)計(jì)指標(biāo)要求，為進(jìn)一步SoC芯片實(shí)驗(yàn)奠定了良好的基礎(chǔ)。
[Abstract]:The digital radar system has become the main development direction of the new generation radar system because of its high precision amplitude-phase orthogonality, anti-jamming, stability and so on. In military and civilian areas such as civil aviation traffic control, land, sea and air surveillance, precision guidance, navigation, At the same time, with the rapid development of microelectronics technology, FPGA and DSP continuously improve their signal processing capability, that is, ASIC can achieve better performance than DSP. And FPGA process faster, Lower power consumption and higher reliability, And the chip with independent intellectual property has a great advantage in price after large-scale production, so it is urgent to design a new generation of digital radar system by using the latest chip system system on chip Chiptechnology. The work of this paper comes from the research project of the ministry, focusing on the IP core design of digital radar receiver signal processing, and the performance optimization and area optimization of the data path. This paper mainly discusses the circuit implementation architecture of income type digital signal processor and time division multiplexing mode, and optimizes the performance and circuit under the time division multiplexing mode. Finally, the data path framework under two optimized conditions is designed. Based on the design experiment of radar receiving channel SoC prototype system and the realization of board level verification platform, the main radar signals are verified and tested. The test results show that the function meets the requirements. Under the SMIC0.13um technology, the main radar signals are verified and tested. In the performance optimization, the maximum if signal throughput is 2GSPS, and the data path area is about 0.05mm2.The experimental results show that the system design and verification platform meets the project design requirements, and lays a good foundation for further SoC chip experiments.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN957.5

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